testbench
Here are 146 public repositories matching this topic...
A verilator testbench framework.
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Feb 2, 2021 - C++
Generate the uvm testbench automatically
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Mar 27, 2024 - Python
Project for the class "Digital Low-level Hardware Systems II" in SystemVerilog.
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Aug 30, 2022 - SystemVerilog
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Mar 14, 2023 - Python
Finite state machine controlled RISC machine
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Feb 27, 2018
Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)
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Apr 9, 2024 - Python
Using Stereo SGM to calculate the disparity map of two images :Stereo Processing by Semiglobal Matching and Mutual Information .
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Feb 3, 2022 - C++
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Nov 29, 2017 - Java
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Aug 5, 2018 - HTML
Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL
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Jan 10, 2022 - SystemVerilog
Remote code unit testing for JupyterHub classrooms
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Jan 23, 2023 - Python
Design for FPGA of a Universal Asynchronous Receiver Transmitter.
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Nov 4, 2021 - C
Diseño de un circuito secuencial con entrada de datos x de 1 bit, una entrada de reset y una entrada de reloj. El sistema es un detector de secuencia que genera una salida z de 1 bit con ‘1’ cuando los últimos cuatro bits recibidos en x son 0101. El circuito se diseña de diversas maneras, cada una de ellas con una descripción en VHDL
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Sep 29, 2022 - VHDL
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