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147 public repositories
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Examples and design pattern for VHDL verification
Updated
Apr 10, 2016
VHDL
basic simulations of digital electronics using vhdl
A test bench that outputs PWM based on a potentiometer input.
Updated
Jan 16, 2017
Arduino
Hardware Simulation using Icarus Verilog EDA Playground for a half adder circuit design and test bench.
Updated
Mar 25, 2017
SystemVerilog
A collection of decoders and their test benches simulated using Verilog.
Updated
Mar 26, 2017
SystemVerilog
Logic Gates to build complex multiplexer and ALU
Updated
Apr 14, 2017
VHDL
A customizable, language-agnostic verification tool written in Perl for managing testbenches and running tests. Licensed under GPLv2.
Updated
Apr 19, 2017
Perl
A Javascript app to test the performance of particles being drawn in the canvas.
Updated
Apr 23, 2017
JavaScript
Functional verification using SystemVerilog's HVL feature
Updated
Sep 21, 2017
SystemVerilog
Aid tools for automation of a Xen hypervisor server. Some of the scripts and configurations here are helpful in setting the environment for developmental testing.
TDD with Vaadin Jumpstart
Updated
Oct 28, 2017
Java
Updated
Nov 29, 2017
Java
Updated
Nov 29, 2017
Java
Updated
Nov 29, 2017
Java
Updated
Nov 29, 2017
Java
Updated
Nov 29, 2017
Java
Updated
Nov 29, 2017
Java
Updated
Nov 29, 2017
Java
A vhdl package for reading and writing bitmap files.
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