testbench

Here are 147 public repositories matching this topic...

Tinker-Twins / AutoDRIVE-AVLDC

AutoDRIVE-AVL DRIVINGCUBE Development & Integration

validation simulation emulation verification stimulation autonomous-driving autonomous-vehicles adas testbench avl co-simulation autodrive digital-twins autodrive-ecosystem avl-drivingcube

Updated May 25, 2024
PureBasic

bbartling / OpenADR-PenTest-Lab

Star

OpenADR-PenTest-Lab is a testbed for learning web app penetration testing in Open Automated Demand Response (OpenADR) systems. It provides a realistic environment for security enthusiasts to practice pen testing on a Virtual Top Node (VTN) server for demand response applications, grid-interactive efficient buildings (GEB), and OpenADR protocols.

react python webapp cybersecurity pentesting testbench bacnet building-automation electricity-prices bacnet-server smartbuildings demandresponse clientservercommunication

Updated May 24, 2024
Python

VUnit / vunit

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VUnit is a unit testing framework for VHDL/SystemVerilog

unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology

Updated May 23, 2024
VHDL

Dragon-Git / icdk

Star

uvm framework generator

template tools generator uvm testbench uvmgen

Updated May 21, 2024
SystemVerilog

Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

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This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

rtl verilog finite-state-machine synthesis vivado systemverilog questasim testbench rtl-design

Updated May 21, 2024
Verilog

ghdl / ghdl

Star

VHDL 2008/93/87 simulator

simulator compiler hardware llvm vhdl gcc ghdl hacktoberfest testbench

Updated May 20, 2024
VHDL

OSVVM / OSVVM

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OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

coverage alerts simulation memory vhdl verification scoreboard methodology verification-methodologies testbench constrained-random memory-model osvvm-blog osvvm coverage-bins transaction-interfaces

Updated May 22, 2024
VHDL

muhammadtalhasami / RTL_Practice

Star

This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.

vhdl rtl verilog testbench muhammadtalhasami-github- 100daysofrtl hardware-coding verilog-practice

Updated May 16, 2024
Verilog

muhammadtalhasami / sv_verilator

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System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool

verification verilog systemverilog testbench verilog-hdl verilator- system-verilog-testbench verilator-testbench

Updated May 12, 2024
C++

eshansurendra / UART-FPGA

Star

UART Transmitter and Receiver implementation for FPGA

fpga embedded-systems verilog uart testbench digital-design quartus-prime systemverilog-hdl

Updated May 6, 2024
SystemVerilog

AutoDRIVE-Ecosystem / AutoDRIVE-AVLDC

Star

AutoDRIVE-AVL DRIVINGCUBE Development & Integration

validation simulation emulation verification stimulation autonomous-driving autonomous-vehicles adas testbench avl co-simulation autodrive digital-twins autodrive-ecosystem avl-drivingcube

Updated May 3, 2024
PureBasic

RDSik / i2c_master

Star

vivado icarus-verilog modelsim testbench verilog-hdl cocotb hdlmake

Updated May 3, 2024
Verilog

RDSik / FPGA_transceiver

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python vivado icarus-verilog modelsim testbench verilog-hdl cocotb hdlmake

Updated May 3, 2024
Verilog

contactpro / UVM_Command_Center

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UVM Command Center - UVM Testbench Builder (DEMO) - Demo of UVM Verification Workflow IDE.

workflow asic fpga templates ide verification eda uvm testbench uvm-command-center uvm-testbench-builder uvm-workflow-ide

Updated Apr 14, 2024
Python

OSVVM / AXI4

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AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components