verilog-hdl
Here are 496 public repositories matching this topic...
Digital Electronics Course Projects
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Jun 7, 2020 - Verilog
Crane Game using Custom Pipelined Processor
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Sep 17, 2022 - VHDL
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Sep 11, 2023 - C
Open Source Verilog Modules
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Jan 25, 2023 - Verilog
In this project, we implemented a different kind of a tic tac toe board game that is played on an FPGA board using its push buttons. We used Verilog HDL to code the project and implemented a VGA interface for visualization.
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Jul 25, 2023 - Verilog
This repository focuses on how to design a PWM Generator with variable Duty cycle
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Nov 22, 2023 - Verilog
Some exercises on verilog.
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Dec 21, 2023 - Verilog
The purpose is to investigate latches, flip-flops, and registers. DA CS 603
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Nov 12, 2018 - VHDL
This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.
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Apr 11, 2021
This repository contains all the work(till task 5) of Soil Monitoring Bot theme(eYRC-2021-22).
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Mar 3, 2022 - Verilog
My Coding Portfolio
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May 3, 2022 - SystemVerilog
Source of USTC CODH Experiment(Advanced Class).
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Aug 23, 2022 - Verilog
Adjustable sinusoidal signal generator based on FPGA
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Nov 15, 2023 - Verilog
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
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May 24, 2024 - Verilog
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