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497 public repositories
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Exploring both MATLAB and Vivado Verilog in designing a Direct Digital Synthesizer (DDS) system with a FIR low-pass filter. This project goes into digital system design, signal processing, and hardware implementation.
Updated
May 26, 2024
Verilog
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
Updated
May 24, 2024
Verilog
VUnit is a unit testing framework for VHDL/SystemVerilog
Updated
May 23, 2024
VHDL
Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.
Updated
May 23, 2024
Verilog
Updated
May 25, 2024
TypeScript
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
Updated
May 20, 2024
Verilog
The repository contains code from a voluntary assignment in the course IDATT2104 Network Programming.
Updated
May 20, 2024
Verilog
This Repository shows the implementation and results of various codes that I write in Verilog HDL
Updated
May 17, 2024
Verilog
Design and Development of AES Encryption and Decryption Modules in Verilog HDL for AES128, AES192, and AES256 Algorithms.
Updated
May 14, 2024
Verilog
This repository contains a collection of basic digital logic gates implemented in Verilog HDL (Hardware Description Language).
Updated
May 14, 2024
Verilog
Updated
May 14, 2024
Perl
This repo contains HDL-bits solutions
Updated
May 13, 2024
Verilog
System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
Verilog code for fundamental combinational and sequential circuits
Updated
May 9, 2024
Verilog
Pre and Post Synthesis Simulation of a Design VSDMemSOC
Updated
May 5, 2024
Verilog
Updated
May 3, 2024
Verilog
Updated
May 3, 2024
Verilog
A Tcl-Library for scripted HDL generation
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Updated
Apr 30, 2024
Verilog
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