Calender Implementation using VHDL on FPGA Board
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Updated
Jun 5, 2024 - VHDL
Calender Implementation using VHDL on FPGA Board
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
Generates multi channels sounds from primitives
Proyecto de Tesis donde se realiza procesamiento digital de audio para hacer una pedalera de efectos de guitarra con la FPGA DE10-Lite
🏛️ [RUSHED🏃♀️] A study on VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language for classroom material.
This repository contains some examples of data acquisition over MATLAB, LabVIEW and VHDL.
App that Generate VHDL Code and Testbench template file
Project for the Reti Logiche Course at @POLIMI, instructed by Prof. Gianluca Palermo during the academic year 2022/23
A 4-bit up-down counter is a digital circuit capable of counting both upwards and downwards in binary, typically controlled by an up/down input signal.
A 4-bit up counter is a digital circuit that increments its output by one with each clock pulse, counting from 0000 to 1111 in binary, and resetting back to 0000 after reaching 1111.
The VHDL code implements a 2x4 decoder, converting two input signals into four output signals based on the input combinations.
The VHDL code implements a 4x1 multiplexer (MUX), selecting one of four input signals based on the two select lines and producing a single output.
The VHDL code describes a D flip-flop with synchronous reset functionality.
Workshop on the course "Methods and Technologies of Computer Engineering" at V. N. Karazin Kharkiv National University
Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.
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