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2,463 public repositories
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Digital logic design tool and simulator
Updated
May 20, 2024
Java
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Updated
May 24, 2024
Python
A FPGA friendly 32 bit RISC-V CPU implementation
Updated
Apr 4, 2024
Assembly
VHDL 2008/93/87 simulator
Updated
May 20, 2024
VHDL
Updated
May 24, 2024
Scala
VUnit is a unit testing framework for VHDL/SystemVerilog
Updated
May 23, 2024
VHDL
Package manager and build abstraction tool for FPGA/ASIC development
Updated
Apr 28, 2024
Python
VHDL course at Brno University of Technology
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Updated
Dec 6, 2023
Verilog
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Updated
May 22, 2024
VHDL
An abstraction library for interfacing EDA tools
Updated
May 17, 2024
Python
Haskell to VHDL/Verilog/SystemVerilog compiler
Updated
May 24, 2024
Haskell
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Updated
Dec 21, 2023
Verilog
A tiny Open POWER ISA softcore written in VHDL 2008
Updated
May 16, 2024
Verilog
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Updated
Nov 29, 2020
VHDL
Hardware Description Languages
VHDL compiler and simulator
Updated
May 24, 2024
VHDL
Support files for participating in a Fomu workshop
Updated
Mar 17, 2024
Verilog
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
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