vhdl
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A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
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May 23, 2024 - Verilog
VHDL grammar for tree-sitter parser generator
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May 22, 2024 - JavaScript
HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
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May 22, 2024 - Python
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May 22, 2024 - VHDL
4 digits 7-segment controller VHDL
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May 22, 2024 - VHDL
Digital Circuit Design projects implemented using VHDL, Verilog
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May 22, 2024 - Verilog
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May 22, 2024 - VHDL
VUnit is a unit testing framework for VHDL/SystemVerilog
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May 22, 2024 - VHDL
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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May 22, 2024 - VHDL
Hardware Description Languages
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May 22, 2024
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May 22, 2024 - VHDL
MCP482x DAC Family VHDL Core
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May 21, 2024 - VHDL
Haskell to VHDL/Verilog/SystemVerilog compiler
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May 22, 2024 - Haskell
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