wishbone-bus
Here are 27 public repositories matching this topic...
Versatile Functional Bus Description Language compiler back-end written in Go.
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May 25, 2024 - VHDL
A small, light weight, RISC CPU soft core
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May 23, 2024 - Verilog
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
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May 23, 2024 - Verilog
Code generation tool for control and status registers
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May 15, 2024 - Ruby
Wishbone controlled I2C controllers
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Feb 22, 2024 - Verilog
A simple, basic, formally verified UART controller
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Jan 29, 2024 - Verilog
A collection of debugging busses developed and presented at zipcpu.com
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Jan 18, 2024 - Verilog
A utility for Composing FPGA designs from Peripherals
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Jan 18, 2024 - C++
A wishbone controlled FM transmitter hack
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Jan 16, 2024 - Verilog
A wishbone controlled scope for FPGA's
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Jan 12, 2024 - Verilog
Bus bridges and other odds and ends
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Jan 12, 2024 - Verilog
Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.
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Apr 23, 2023 - VHDL
Simple UART controller for FPGA written in VHDL
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Aug 7, 2021 - VHDL
A collection of formal properties for hardware buses, and cores using them.
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Feb 22, 2021 - Verilog
A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91
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Nov 6, 2020 - Python
RISC-V Ibex core with Wishbone B4 interface
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Dec 24, 2019 - HTML
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