A C++ ostream class (client) and a Python script (server) for writing a file on a remote system from a client using lwIP stack.
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Updated
May 27, 2024 - C
A C++ ostream class (client) and a Python script (server) for writing a file on a remote system from a client using lwIP stack.
A TFTP server running on Zynq-7000
Zynq-7000 PS side drivers for SLCR Registers.
Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.
Notes after working with Zynq platform using vivado and petalinux
ILI9488 TFT SPI display library for Xilinx SoC and FPGA
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
Firmware with overclock support for LibreSDR (PlutoSDR clone with Zynq 7020), 27.5 MSPS sample rate over Gigabit Ethernet with libiio/PlutoSDR API
Dual-Mode PSK Transceiver on SDR With FPGA
This is my sandbox for exploring the use of C++ to develop projects for the AMD (Xilinx) Zynq. One of the aims is to begin the process of creating a range of c++ drivers that can be re-used for other Zynq-7000/Ultrascale/Microblaze designs. The IDE is Vivado/Vitis 2023.2 (Classic version).
This is my sandbox for experimenting with the features offered by the AMD (Xilinx) FreeRTOS port. The main platform used is the Digilent Zybo-z7-20. The implemented system is quite simple, comprising a range of GPIO features (LEDs, buttons, switches, and test outputs for monitoring) and two UART communication channels.
This is xc7z020clg400 FPGA hardware core board design
Global Dark Mode for ALL apps on ANY platforms.
Real-Time Operating System (RTOS) for Xilinx Zynq-7000 Cortex-A9 (ARMv7-A) multi-core SoCs (ZedBoard, PicoZed, MicroZed and similars) based on the ARINC 653 Part 1 specification
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