Accessing PCIe endpoint BAR on NXP iMX8MM #71972
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davidfenger-ivl
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Hi David, My understanding is it works well when running Linux on imx8mm and PCIe working in EP mode, then you try to replace the Linux with Zephyr on imx8mm to drive PCIe EP, right? For the host PC access to the imx8mm PCIe EP's Config space, it uses ID addressing, so it does not depend on the mapping on imx8mm. but you need to do some setup in EP side, before host PC to enumerate the PCIe buses. Please refer to the Linux imx pcie driver. |
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I'm trying to build for a system that's using the NXP iMX8MM PCIe port in endpoint mode. To make my life a little easier, I'm letting Linux do the heavy lifting of getting the PCIe endpoint up and running. It can see and access the BAR registers, and I have a driver on the host PC that can read and write them, and sees the same values as the linux-side endpoint function writes.
However, I need to access these registers (and mostly manage DMA) with the lower latency jailhouse and zephyr offers. So I need to figure out how to talk to the BAR. Yes, this is something of a hack, but I don't see any drivers for the PCIe IP NXP is using. If they exist somewhere, a pointer to how to set it up would be very helpful.
I can use device_map to access the PCIe device registers at 0x33800000, and I can see how the iATU has been configured. It looks like it's pointing at 0x18000000, which is marked as PCIe address space in the reference manual and Linux device tree. But when I try to map that, it does not work - trying to read from it causes the host PC (other end of the PCIe link) to bluescreen due to a DMA violation.
Obviously I need to either access different memory or map it in a different way. Any advice or pointers on how to do this would be most welcome.
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