bluesim simulation result is different from verilog simulation, does bluesim have bug implementing UInt#(n) when n is big (eg., 72)?

[daveMmd]

I write a Action function:

function Action write_mce_mask(UInt#(72) mce_id, UInt#(72) wr_data);
return action
$display("write mce mask: %d %h", mce_id, wr_data);
mce_mask_vec[mce_id] <= wr_data;
endaction;
endfunction

the results of bluesim and verilog simulation are different, the former is:
"
write mce mask: 0 ffffff000000000000
write mce mask: 4703919738795935662081 ffff00000000000000
write mce mask: 4703919738795935662082 ffffffffff00000000
write mce mask: 4703919738795935662083 ffffffff0000000000
write mce mask: 4703919738795935662084 fffffff00000000000
"

while the latter is:
"
write mce mask: 0 ffffff000000000000
write mce mask: 1 ffff00000000000000
write mce mask: 2 ffffffffff00000000
write mce mask: 3 ffffffff0000000000
write mce mask: 4 fffffff00000000000
"

verilog simulation result is right. Is there a bug in bluesim?

[quark17]

I am unable to replicate your issue. Can you provide a complete example, that I can compile and run? You show a function, but you don't show how it is called or the module context around it.

I made the following example:

(* synthesize *)
module mkTest ();

  Reg#(UInt#(72)) rg_id <- mkReg(0);

  rule r;
    $display("id = %d", rg_id);
    rg_id <= rg_id + 1;
    if (rg_id > 5) $finish(0);
  endrule

endmodule

But the output is the same with both Icarus Verilog and Bluesim:

id =                      0
id =                      1
id =                      2
id =                      3
id =                      4
id =                      5
id =                      6

Can you compile and run this simulation in Bluesim and see if you get different results?

Also, what OS and architecture are you running on? It may be due to the C++ compiler on your system.