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181 Open 114 Closed
181 Open 114 Closed
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Issues list

Failures with compilation on raspberry-pi 5
#696 opened May 10, 2024 by mycroft92
-remove-unused-modules flag doesn't work with mkProbe module provided in std library
#695 opened May 8, 2024 by myrfy001
doc example for mkUniqueWrapper2
#694 opened Apr 23, 2024 by postoroniy
6
Type synonyms with phantom parameters can lead to strange behaviors (E.g., compiler hang)
#692 opened Apr 16, 2024 by rossc719g
4
Bluesim divide-by-zero behavior is inconsistent on arm64 bluesim Relates to Bluesim
#688 opened Apr 6, 2024 by quark17
2
Unexpected behavior in Stmt sequence when using par
#685 opened Mar 25, 2024 by arjenroodselaar
2
expandPorts.tcl has hardcoded paths which do not exist.
#683 opened Mar 13, 2024 by jahagirdar
1
Unexpected syntax error
#682 opened Mar 11, 2024 by metanest
1
Verilog import fails in macro substitution
#679 opened Mar 1, 2024 by yannickl96
2
Bluesim's symbol-probing interface has wrong values for FIFO bluesim Relates to Bluesim bug Something isn't working good first issue Good for newcomers
#677 opened Feb 27, 2024 by quark17
Internal Compiler Error when quoting a character value.
#673 opened Feb 15, 2024 by yseulp
@mieszko
4
Static check of file descriptor argument to tasks like $fgetc enhancement New feature or request error-messages Improvements to user messages
#668 opened Jan 29, 2024 by c-93
3
Missing Ord Bool instance
#665 opened Jan 17, 2024 by RyanGlScott
7
-dparsed produces invalid BSV module function that takes another module as an argument
#663 opened Jan 14, 2024 by RyanGlScott
1
2
-dparsed output produces invalid register updates with BSV
#662 opened Jan 14, 2024 by RyanGlScott
2
module verilog does not allow sharing ports among conflicting methods ICE Internal compiler error
#658 opened Dec 28, 2023 by mieszko
bsc ignores always_ready when checking for duplicate wires ICE Internal compiler error
#657 opened Dec 27, 2023 by mieszko
Bluesim leaves junk in loaded registers if the full range of hex digits isn't specified
#650 opened Dec 13, 2023 by nanavati
3
bluesim simulation result is different from verilog simulation, does bluesim have bug implementing UInt#(n) when n is big (eg., 72)?
#648 opened Nov 30, 2023 by daveMmd
1
Better positions for kind-mismatch errors error-messages Improvements to user messages typecheck Relates to the typecheck stage of compilation
#647 opened Nov 28, 2023 by quark17
mkRegFileFullLoad does not actually Load if index_t is 0 bits.
#643 opened Nov 9, 2023 by rossc719g
8
Any way to get the RDY signal for a method?
#637 opened Oct 30, 2023 by myrfy001
7
Support superclasses with (dependent) type variables not in the base typeclass bug Something isn't working enhancement New feature or request typecheck Relates to the typecheck stage of compilation
#633 opened Oct 23, 2023 by quark17
2
consider a name different from "core" inside the bin directory
#632 opened Oct 23, 2023 by kenta2
assertion checks should have knowledge of rwire/creg internals enhancement New feature or request
#631 opened Oct 20, 2023 by quark17
5
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