2018/10/30: round 1

2023/10/19 - 11/6: round 2

2024/2/28: round 3

==================================

Reference:

https://github.com/riscv/learn

https://github.com/TheThirdOne/rars

https://github.com/LC-John/RISCV-Simulator

online content(there is a verilog implementation of a RISC-V CPU, study it very carefully)

Solution Manual for RISC-V Edition

Solution to Appendix A

http://chinetti.me/classes/ece485/cd%20content/Advanced-Content-and-Appendixes.html

https://github.com/dmohindru/cod5e

https://www.studocu.com/ko/document/konkuk-university/%EC%BB%B4%ED%93%A8%ED%84%B0%EA%B5%AC%EC%A1%B0/computerorganizaion-design-5th-solution/9639022

TODO:

use verilog and chisel respectively to implement a RISC-V CPU to run xv6-riscv