virtio-fpga-bridge

A platform for emulating Virtio frontend and backend bridging with FPGAs.

Introduction

With the Qemu-HDL Cosim framework, it is now possible to run the full system emulation of BM-Hive (Alibaba Cloud's X-Dragon, "Shenlong" in Chinese) on a single x86 PC.

BM-Hive architecture

virtio-fpga-bridge

The Virtio frontend runs on the 1st x86(Qemu), and the Virtio backend runs on the 2nd x86(Qemu). FPGA(HDL Sim) plays the role of bridging/synchronizing the frontend and backend, with shadow vrings and DMAs.

There are two PCIe-EP IPs instantiated in the FPGA logic. The EP facing the 1st x86 is an implementation of the standard Virtio protocol. And there is no driver modification needed in the 1st x86 OS. The EP interfacing with the 2nd x86 is an implementation of a custom protocol, handling CSR/Mailbox registers and DMAs. And user space drivers, such as ixy, DPDK and SPDK, are needed for this interface.

Discussion

System topology

With Virtio's Virtqueue handling implemented in FPGA, there are many possible combinations of how the system can be constructed.

HW limitations

BM-Hive requires special HW PCB board design, on which the x86 system is not available for many PCIe FPGA development boards. Adding a soft-core CPU inside the FPGA is an interesting option.