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[libcpu/arm64] add C11 atomic ticket spinlock #8882

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merged 2 commits into from
May 16, 2024

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@polarvid polarvid commented Apr 29, 2024

拉取/合并请求描述:(PR description)

[

为什么提交这份PR (why to submit this PR)

Replace the former implementation of flag-based spinlock which is unfair.

Besides, C11 atomic implementation is more readable (it's C anyway),
and maintainable. Cause toolchain can use their builtin optimization and tune for
different micro-architectures. For example armv8.5 introduces a better instruction.
the compiler can help with that when it knows you target platform in support of it).

你的解决方案是什么 (what is your solution)

请提供验证的bsp和config (provide the config and bsp)

  • BSP: RK3568, QEMU
  • .config:
  • action:

]

当前拉取/合并请求的状态 Intent for your PR

必须选择一项 Choose one (Mandatory):

  • 本拉取/合并请求是一个草稿版本 This PR is for a code-review and is intended to get feedback
  • 本拉取/合并请求是一个成熟版本 This PR is mature, and ready to be integrated into the repo

代码质量 Code Quality:

我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:

  • 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
  • 代码风格正确,包括缩进空格,命名及其他风格 Style guide is adhered to, including spacing, naming and other styles
  • 没有垃圾代码,代码尽量精简,不包含#if 0代码,不包含已经被注释了的代码 All redundant code is removed and cleaned up
  • 所有变更均有原因及合理的,并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
  • 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
  • 代码是高质量的 Code in this PR is of high quality
  • 已经使用formatting 等源码格式化工具确保格式符合RT-Thread代码规范 This PR complies with RT-Thread code specification

@polarvid polarvid force-pushed the shell/generic-spinlock branch 4 times, most recently from b12a82d to a9fc6aa Compare April 30, 2024 02:04
Replace the former implementation of flag-based spinlock which is unfair

Besides, C11 atomic implementation is more readable (it's C anyway),
and maintainable. Cause toolchain can use their builtin optimization and
tune for different micro-architectures. For example armv8.5 introduces a
better instruction. The compiler can help with that when it knows your
target platform in support of it.

Signed-off-by: Shell <smokewood@qq.com>
@polarvid polarvid marked this pull request as ready for review May 9, 2024 05:24
@polarvid polarvid requested a review from Guozhanxin as a code owner May 9, 2024 05:24
ORR X0, X0, #0x38
MSR HCR_EL2, X0
B 0f
MRS X0, HCR_EL2
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可以对这份代码做些代码对齐

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@polarvid polarvid May 16, 2024

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同样在 pr #8950 调整了

@polarvid polarvid mentioned this pull request May 16, 2024
9 tasks
@BernardXiong BernardXiong merged commit e25fc8b into RT-Thread:master May 16, 2024
45 checks passed
zhuzhuzhus pushed a commit to zhuzhuzhus/rt-thread that referenced this pull request May 21, 2024
[libcpu/arm64] add C11 atomic ticket spinlock (RT-Thread#8882)

* [libcpu/arm64] add C11 atomic ticket spinlock

Replace the former implementation of flag-based spinlock which is unfair

Besides, C11 atomic implementation is more readable (it's C anyway),
and maintainable. Cause toolchain can use their builtin optimization and
tune for different micro-architectures. For example armv8.5 introduces a
better instruction. The compiler can help with that when it knows your
target platform in support of it.

Signed-off-by: Shell <smokewood@qq.com>

* fixup: RT_CPUS_NR

---------

Signed-off-by: Shell <smokewood@qq.com>
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2 participants