Issues: SystemRDL/PeakRDL-regblock
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[BUG] Genus unsynthesizable error on rising/falling edge interrupt field
#113
opened May 25, 2024 by
BertVerrycken
1 task done
[BUG] memory size is not calulated correctly
invalid
This doesn't seem right
#110
opened May 23, 2024 by
arnonsha
More optimized readback stage RTL generation
invalid
This doesn't seem right
wontfix
This will not be worked on
#103
opened Apr 27, 2024 by
Blebowski
hwset on multibit field
feature request
New feature or request
#99
opened Apr 16, 2024 by
darrylring
unconditional is None # Can only have one unconditional assignment per field
bug
Something isn't working
#93
opened Apr 3, 2024 by
xachb
Casting For-Loop Iterator to Match Address Width in Decoding Logic
#92
opened Apr 2, 2024 by
leolitenstorrent
Raising an error for unauthorized read or write
feature request
New feature or request
#76
opened Dec 11, 2023 by
imerkado91
During export, check for identifier collisions in output
feature request
New feature or request
#73
opened Nov 7, 2023 by
amykyta3
VHDL Package Compatibilty
feature request
New feature or request
#61
opened Aug 16, 2023 by
eddlestar
Feature Request: Option to remove buffer stage from AXI read/write
feature request
New feature or request
#47
opened Jun 12, 2023 by
leolitenstorrent
Add support for write broadcasting
feature request
New feature or request
#37
opened Apr 12, 2023 by
amykyta3
Emit Parametrized PeakRDL output
feature request
New feature or request
#33
opened Apr 4, 2023 by
galaviel
Add support for alias registers
feature request
New feature or request
#32
opened Mar 25, 2023 by
amykyta3
Add option to generate a UVM HDL Path overlay
feature request
New feature or request
#15
opened Jun 23, 2022 by
amykyta3
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