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Trying to parameterize a Verilog module that name is not lower-case causes error. #944

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piotrva opened this issue Jul 12, 2023 · 0 comments · May be fixed by #945
Open

Trying to parameterize a Verilog module that name is not lower-case causes error. #944

piotrva opened this issue Jul 12, 2023 · 0 comments · May be fixed by #945

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@piotrva
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piotrva commented Jul 12, 2023

When executing a Library.module(), when a Verilog module has non-lower-case name an error occurs.
This is due to the fact that both Library.entity() (VHDL) and Library.module() (Verilog) generate call to Library.test_bench(), that makes the name always lower-case.

Above calls trying to parameterize any non-lower-case Verilog module to fail.
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Fix issues when trying to parameterize Verilog modules piotrva/vunit
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