Add Block Design support for simulation

[SzymonHitachi]

Closes #963

Added block design parsing and generation based on https://gitlab.com/tsfpga/tsfpga/-/issues/74.

1. Requires creating tcl file through write_bd_tcl for open block designs
2. Resulting tcl should be located together with other ip_cores

[LudvigVidlid]

@LarsAsplund, this is related to issue #172 , which was closed as out-of-scope of VUnit. I think it's closely enough related to the standard IP core generation already present, especially considering the change is small. But in case you disagree we could add this support in tsfpga instead.

[jh16g15]

This is great, thanks!

Perhaps I'm missing something, but I found in Vivado 2019.1 if a Block Design isn't instantiated as part of the current simulation "top" module then get_files -used_in simulation -compile_order sources *${bd}* doesn't return any files.

This can be resolved by setting each Block Design as the top module for simulation in turn, replacing the last part of extract_compile_order.tcl with the following:

set old_sim_top [get_property top [get_filesets sim_1]]
set old_sim_top_lib [get_property top_lib [get_filesets sim_1]]
foreach bd [get_bd_designs -quiet] {
    set_property top ${bd} [get_filesets sim_1];
    update_compile_order -fileset sim_1
    foreach src_file [get_files -used_in simulation -compile_order sources *${bd}*] {
        set library [get_property LIBRARY ${src_file}]
        set file_type [get_property FILE_TYPE ${src_file}]
        puts ${file_out} "${library},${file_type},${src_file}"
    }
}
set_property top ${old_sim_top} [get_filesets sim_1]
set_property top_lib ${old_sim_top_lib} [get_filesets sim_1]
update_compile_order -fileset sim_1

[SzymonHitachi]

I'm curious why would we actually want to compile it if it's not instantiated then? Or am I misunderstanding you?

I have checked my simulation and for me the BD is instantiated in a nested way: tb/dut/bd - do you say that if it's nested deeper than this way it will fail?

[jh16g15]

Sorry, I explained poorly - it is if it's instantiated in a different (non-currently top) testbench that we still want to compile it.

Perhaps it's specific to my project - it's been going for many years with multiple parts of the system (frontend, backend) that I'm attempting to get all into a single simulation framework (hence VUnit😄)

We have a variety of testbenches and are currently migrating from the Vivado simulator to using VUnit with Modelsim/Questasim - this means that the current simulation top could be set to a smaller unit testbench that doesn't contain any/all the BDs, depending on whoever last simulated and committed the project TCL.

I'm aiming to remove the dependency on requiring the full integration testbench to be set as the top simulation source in Vivado before VUnit is run, to add more robustness to the BD/IP extraction.

So for example, if I have the following structure, and want to run all the testbenches with VUnit:

tb_unit_small (set as Top in the vivado project)
    unit_small

tb_full_backend_design
     full_backend_design
        axi_fun_interconnect.bd
        ...

tb_other_part_of_system
   other_part_of_system.bd

Vivado won't pick up the simulation files for axi_fun_interconnect.bd or other_part_of_system.bd while tb_unit_small is set as the top simulation file (and unless I have a testbench that instantiates both axi_fun_interconnect.bd and other_part_of_system.bd, AND that testbench is set as the top simulation source in the vivado project, VUnit will have mysteriously failing/passing tests due to component not bound as Modelsim doesn't have the simulation files for everything)

[SzymonHitachi]

I'm still confused. If you have tb_unit_small compiled and tested then you dont instantiate the BD thus you dont have it nor want it. And thats ok. You dont want to compile stuff you dont use right?

But when you set e.g. tb_full_backend_design as top it should istantiate the underlying BD and grab it. Does it not?

[jh16g15]

When I set the simulation I want to run as top manually, yes, everything works fine - it's when I want to use VUnit to run all testbenches in one go that I need to ensure all files needed for any of the simulations are in the VUnit compile order.

(IE for running regression tests, which currently I run manually but eventually will be happening in CI when I get a gitlab runner set up)

[SzymonHitachi]

When I set the simulation I want to run as top manually, yes, everything works fine - it's when I want to use VUnit to run all testbenches in one go that I need to ensure all files needed for any of the simulations are in the VUnit compile order.

(IE for running regression tests, which currently I run manually but eventually will be happening in CI when I get a gitlab runner set up)

Ok I understand now. So your proposed solution adds setting the BD as top file temporary, and then returns to original top after its done? What if the fileset is not named sim_1?

[jh16g15]

Yes, exactly 👍

I haven't used multiple Vivado simulation sets before, but I've had a quick play around.

We can use

set current_simset [current_fileset -simset]

to get whatever the current simulation set is.

So replacing sim_1 with $current_simset gives us

set current_simset [current_fileset -simset]
set old_sim_top [get_property top [get_filesets $current_simset]]
set old_sim_top_lib [get_property top_lib [get_filesets $current_simset]]
foreach bd [get_bd_designs -quiet] {
    set_property top ${bd} [get_filesets $current_simset];
    update_compile_order -fileset $current_simset
    foreach src_file [get_files -used_in simulation -compile_order sources *${bd}*] {
        set library [get_property LIBRARY ${src_file}]
        set file_type [get_property FILE_TYPE ${src_file}]
        puts ${file_out} "${library},${file_type},${src_file}"
    }
}
set_property top ${old_sim_top} [get_filesets $current_simset]
set_property top_lib ${old_sim_top_lib} [get_filesets $current_simset]
update_compile_order -fileset $current_simset

This would handle the simulation fileset not being called sim_1. What it wouldn't do is grab all the BDs if the current simset was created without "add all design sources for simulation", or if there were simulation-only BDs in the project that weren't added to the simulation fileset currently selected (in the case of multiple simulation filesets).

But then perhaps covering those cases isn't necessary as the workaround of "make sure all BDs are in your simulation set" doesn't feel onerous or unreasonable to me (I assume if a project is using VUnit for simulation having multiple different simulation sets in Vivado becomes less useful anyway).

[SzymonHitachi]

Hi @LarsAsplund any update on merging this fix?

[SzymonHitachi]

Updated the fork with newest @LarsAsplund to try to rerun the actions for merge.