riscv-multi-core-lotr

Accelerator for multi-thread processing IP.  
LOTR: Lord-Of-The-Ring
Based on a Ring architecture to share all memory regions between threads, cores & other devices.

The Design is loaded to the DE10Lite FPGA.

Writing to FPGA IO - LED:

Writing to Display - accessable with LOAD/STORE from any Thread.

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The reposetory has 4 main projects:

1) GPC_4T - RISCV core RV32I/E. with 4 HW threads  

Written in System verilog.
Main Blocks:

1. Core - 4 HW thread. Compatible with RV32I/E.
2. I_MEM (Instruction Memory). 4KB of SRAM memory with dual access (core & Fabric).
3. D_MEM (Data Memory) - 4KB of SRAM memory with duel access (core & Fabric).  
   Devided to: Compiler Scratchpad(.data.bss.rodata) + Shared MEM Space + CR Space (Control Registers)

2) RC - Ring Controller  

Written in SystemVerilog.
Ring EP (EndPoint) to Manage the cores & ring RD/WR traffic. Main logic:

1. A2F buffer (Agent2Fabric).
2. F2A buffer (Fabric2Agent).
3. Ring output Arbiter. (A2F,F2A,Ring input)

3) LOTR: Integration Model, Lord-Of-The-Ring  

Written in SystemVerilog.   Instantiating the Cores and Ring into a single Fabric IP design.   Main Blocks:  

1. GPC_4T core with its own "local" 4k memory - interface with the RC (ring controller).
2. RC - Ring EndPoint to arbitrate requests - interface with the other RC and the core.
   The GPC&RC are always coupled and have a unique "ID".
   In the fabric, we can link many RC to each other.
   which will enable the Many-core Ring Fabric Design.

4) Software stack for multi-thread processing  

Written in C and compiled using the RISCV toolchain (rv32i/e).
Proof of concept for multi-thread applications for the multi-core design.

1. Design programs that can run on the 4 threaded core and share data between threads.
2. Design programs that can be run on many cores, utilize the threads in each core, and share data between all cores.

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Pointers To Get Started

Getting Started

To see your build and run options, run the following command:
python build.py -h
example:
python build.py -dut 'lotr' -debug -tests 'wip' -app
Will compile using gcc the program called 'wip', which then can be used to load the FPGA with the uart:
cd source/uart_io/pyterminal/src
Then:
python uart_term.py < sequence_abd/load_wip.txt
will load the FGPA with the program 'wip' and run it.

Prerequisite

Before you start, make sure you have the following tools and software installed:

• RISCV gcc releases & install, a Windows gcc for RISCV ISA.
• Intel design SW for windows , modelsim + quartus + MAX10 (de10-lite). used to compile, simulate & load to FPGA the HW systemverilog design.

Recommendations

To make your experience smoother, we recommend installing the following tools:

• GitBash, a Windows version of Git that includes a "Unix-like" shell.

• Visual Studio Code, a code editor that supports many programming languages.

• RISCV GCC for windows: TODO - write a script to download and install the toolchain.

• Compilation and Simulation:
  Using Modelsim - https://fpgasoftware.intel.com/

The HW & SW in the project:

• Core - GPC_4T - RTL Design:
  HAS (High-Level-Architecture-Specification):
  RISCV Spec - https://github.com/amichai-bd/riscv-multi-core-lotr/blob/master/doc/GPC_4T_doc/riscv-spec-20191213.pdf
  HW Spec -
  MAS (Micro-Level-Architecture-Specification):
  see under documentation

• Ring Controler - RC - RTL Design:
  HAS (High-Level-Architecture-Specification):
  see under documentation
  MAS (Micro-Level-Architecture-Specification):

• Fabric - LOTR - (Integration Model) - RTL Design:
  HAS (High-Level-Architecture-Specification):
  MAS (Micro-Level-Architecture-Specification):

• uart_io tile- RTL Design & python terminal for FPGA IO:
  HAS (High-Level-Architecture-Specification):
  MAS (Micro-Level-Architecture-Specification):

- SW Stack:

• Validation: