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Incorrectly added Reverse(Top) Value due to edge case in merge logic #4245
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fmagin
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Oct 27, 2023
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Description
Assuming you have two blocks
pred_1
andpred_2
that both precede some blocknode
.If you are loading a static address for the first time in
pred_1
,SimEngineRDXVEX
will retrieve the value fromproject.loader.memory
and then store it viastate.store
:angr/angr/analyses/reaching_definitions/engine_vex.py
Lines 444 to 468 in cbeace5
But on merging the merge code treats the address from the
pred_2
state as anunconstrained_in
because it was never accessed inpred_2
and so isn't part of that page in the memory state frompred_2
yet.angr/angr/storage/memory_mixins/paged_memory/pages/mv_list_page.py
Lines 172 to 182 in cbeace5
This will then later mean that a
Top
value is generated for this location when merging the state, which is then stored in memory endianess (and thus flipped), resulting inReverse(Top)
being read from that location if this address is accessed insidenode
, or subsequent blocks.Steps to reproduce the bug
I can't share the binary and code that triggers this, but I hope the error description is sufficient to understand why this bug is happening.
Environment
No response
Additional context
No response
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