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  • Kwangwoon University
  • Seoul, South Korea

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Pinned

  1. Pipelined-RV32I Pipelined-RV32I Public

    Verilog Implementation of 5-stage pipelined RISC-V RV32I Instruction Set Architecture

    Verilog 1

  2. Single-Cycle-RV32I Single-Cycle-RV32I Public

    Verilog Implementation of RISC-V RV32I Instruction Set Architecture

    Verilog