[LoongArch64] Add some R2R missing codes. (#101480)

src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs

@@ -97,6 +97,10 @@ public static string GetHardwareIntrinsicId(TargetArchitecture architecture, Typ
                 if (potentialType.Namespace != "System.Runtime.Intrinsics.Arm")
                     return "";
             }
+            else if (architecture == TargetArchitecture.LoongArch64)
+            {
+                return "";
+            }
             else if (architecture == TargetArchitecture.RiscV64)
             {
                 return "";

src/coreclr/tools/Common/Compiler/VectorFieldLayoutAlgorithm.cs

@@ -58,6 +58,11 @@ public override ComputedInstanceFieldLayout ComputeInstanceLayout(DefType defTyp
                     // 16-byte alignment for __m256.
                     alignment = new LayoutInt(16);
                 }
+                else if (defType.Context.Target.Architecture == TargetArchitecture.LoongArch64)
+                {
+                    // TODO-LoongArch64: Update alignment to proper value when implement LoongArch64 intrinsic.
+                    alignment = new LayoutInt(16);
+                }
                 else if (defType.Context.Target.Architecture == TargetArchitecture.RiscV64)
                 {
                     // TODO-RISCV64: Update alignment to proper value when we implement RISC-V intrinsic.
@@ -86,6 +91,11 @@ public override ComputedInstanceFieldLayout ComputeInstanceLayout(DefType defTyp
                     // 16-byte alignment for __m256.
                     alignment = new LayoutInt(16);
                 }
+                else if (defType.Context.Target.Architecture == TargetArchitecture.LoongArch64)
+                {
+                    // TODO-LoongArch64: Update alignment to proper value when implement LoongArch64 intrinsic.
+                    alignment = new LayoutInt(16);
+                }
                 else if (defType.Context.Target.Architecture == TargetArchitecture.RiscV64)
                 {
                     // TODO-RISCV64: Update alignment to proper value when we implement RISC-V intrinsic.

src/coreclr/tools/Common/JitInterface/CorInfoImpl.cs

@@ -415,9 +415,10 @@ private CompilationResult CompileMethodInternal(IMethodNode methodCodeNodeNeedin
             if (codeSize < _code.Length)
             {
                 if (_compilation.TypeSystemContext.Target.Architecture != TargetArchitecture.ARM64
+                    && _compilation.TypeSystemContext.Target.Architecture != TargetArchitecture.LoongArch64
                     && _compilation.TypeSystemContext.Target.Architecture != TargetArchitecture.RiscV64)
                 {
-                    // For xarch/arm32/RiscV64, the generated code is sometimes smaller than the memory allocated.
+                    // For xarch/arm32/LoongArch64/RiscV64, the generated code is sometimes smaller than the memory allocated.
                     // In that case, trim the codeBlock to the actual value.
                     //
                     // For arm64, the allocation request of `hotCodeSize` also includes the roData size

src/coreclr/tools/Common/JitInterface/LoongArch64PassStructInRegister.cs

@@ -29,12 +29,6 @@ public static uint GetLoongArch64PassStructInRegisterFlags(TypeDesc typeDesc)
                 return (uint)StructFloatFieldInfoFlags.STRUCT_NO_FLOAT_FIELD;
             }
 
-            //// The SIMD Intrinsic types are meant to be handled specially and should not be passed as struct registers
-            if (typeDesc.IsIntrinsic)
-            {
-                throw new NotImplementedException("For LoongArch64, SIMD would be implemented later");
-            }
-
             MetadataType mdType = typeDesc as MetadataType;
             Debug.Assert(mdType != null);
 

src/coreclr/tools/aot/ILCompiler.Diagnostics/PerfMapWriter.cs

@@ -136,6 +136,7 @@ private static PerfmapTokensForTarget TranslateTargetDetailsToPerfmapConstants(T
                 TargetArchitecture.X64 => PerfMapArchitectureToken.X64,
                 TargetArchitecture.X86 => PerfMapArchitectureToken.X86,
                 TargetArchitecture.RiscV64 => PerfMapArchitectureToken.RiscV64,
+                TargetArchitecture.LoongArch64 => PerfMapArchitectureToken.LoongArch64,
                 _ => throw new NotImplementedException(details.Architecture.ToString())
             };
 

src/coreclr/tools/aot/ILCompiler.Diagnostics/ReadyToRunDiagnosticsConstants.cs

@@ -20,6 +20,7 @@ public enum PerfMapArchitectureToken : uint
     X64 = 3,
     X86 = 4,
     RiscV64 = 5,
+    LoongArch64 = 6,
 }
 
 public enum PerfMapOSToken : uint

src/coreclr/vm/methodtablebuilder.cpp

@@ -10051,6 +10051,9 @@ void MethodTableBuilder::CheckForSystemTypes()
                     // The Procedure Call Standard for ARM 64-bit (with SVE support) defaults to
                     // 16-byte alignment for __m256.
 
+                    pLayout->m_ManagedLargestAlignmentRequirementOfAllMembers = 16;
+    #elif defined(TARGET_LOONGARCH64)
+                    // TODO-LoongArch64: Update alignment to proper value when implement LoongArch64 intrinsic.
                     pLayout->m_ManagedLargestAlignmentRequirementOfAllMembers = 16;
     #elif defined(TARGET_RISCV64)
                     // TODO-RISCV64: Update alignment to proper value when we implement RISC-V intrinsic.
@@ -10074,6 +10077,9 @@ void MethodTableBuilder::CheckForSystemTypes()
 
                     pLayout->m_ManagedLargestAlignmentRequirementOfAllMembers = 16;
 
+    #elif defined(TARGET_LOONGARCH64)
+                    // TODO-LoongArch64: Update alignment to proper value when implement LoongArch64 intrinsic.
+                    pLayout->m_ManagedLargestAlignmentRequirementOfAllMembers = 16;
     #elif defined(TARGET_RISCV64)
                     // TODO-RISCV64: Update alignment to proper value when we implement RISC-V intrinsic.
                     // RISC-V Vector Extenstion Intrinsic Document

src/libraries/System.Reflection.Metadata/src/System/Reflection/PortableExecutable/PEHeaderBuilder.cs

@@ -105,7 +105,7 @@ public static PEHeaderBuilder CreateLibraryHeader()
             return new PEHeaderBuilder(imageCharacteristics: Characteristics.ExecutableImage | Characteristics.Dll);
         }
 
-        internal bool Is32Bit => Machine != Machine.Amd64 && Machine != Machine.IA64 && Machine != Machine.Arm64 && Machine != Machine.RiscV64;
+        internal bool Is32Bit => Machine != Machine.Amd64 && Machine != Machine.IA64 && Machine != Machine.Arm64 && Machine != Machine.LoongArch64 && Machine != Machine.RiscV64;
 
         internal int ComputeSizeOfPEHeaders(int sectionCount) =>
             PEBuilder.DosHeaderSize +

src/tasks/Crossgen2Tasks/ResolveReadyToRunCompilers.cs

@@ -233,6 +233,9 @@ private static bool ExtractTargetPlatformAndArchitecture(string runtimeIdentifie
                 case "riscv64":
                     architecture = Architecture.RiscV64;
                     break;
+                case "loongarch64":
+                    architecture = Architecture.LoongArch64;
+                    break;
                 default:
                     return false;
             }
@@ -391,6 +394,7 @@ private static string ArchitectureToString(Architecture architecture)
                 Architecture.Arm => "arm",
                 Architecture.Arm64 => "arm64",
                 Architecture.RiscV64 => "riscv64",
+                Architecture.LoongArch64 => "loongarch64",
                 _ => null
             };
         }