add intersphinx target pySystemVerilogModel

edaa-org · Sep 26, 2021 · 19f1410 · 19f1410
1 parent d90c154
commit 19f1410
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/conf.py b/conf.py
@@ -179,6 +179,7 @@ def _LatestTagName():
 	'python':               ('https://docs.python.org/3', None),
 	'osvb':                 ('https://umarcor.github.io/osvb', None),
 	'pyVHDLModel':          ('https://vhdl.github.io/pyVHDLModel', None),
+	'pySystemVerilogModel': ('https://edaa-org.github.io/pySystemVerilogModel', None),
 }