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Playground to explore and compare how configuration is handled by different tools for development of VHDL projects

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VHDL project configuration

This repository is a playground for exploring and comparing how configuration is handled by different tools for development of (V)HDL projects. The main motivation is hopefully finding a universal format/procedure for reducing duplication. The repository is organised as follows:

Tools/Toolchains

The following table shows which tool examples were contributed to this repository already. Some of them are used in some modules only (yet).

demo leds full_adder uart
GHDLSynth Yes *1
VUnit Yes
pyFPGA Yes *2
  • *1 Icestick only
  • *2 Vivado and generic Yosys only

Target boards and compatible/tested modules

Not all the modules were used in all the boards yet. The following list shows the combinations that are known to work:

  • icestick, ice40hx8k
    • leds/src/leds.vhdl leds/src/$arch | for arch in blink fixed multi1 multi2 rotate1 rotate2 rotate3 rotate4 spin
  • icestick
    • uart/src/uart_tx.vhd uart/src/uart_tx.vhd uart/src/uart_top.vhd
  • ecp5-evn, orange-crab
    • demo/src/demo.vhd

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Playground to explore and compare how configuration is handled by different tools for development of VHDL projects

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