Pinned

1. corsair corsair Public

   Control and Status Register map generator for HDL projects

   Python 90 26

2. openocd-svd openocd-svd Public

   Standalone OpenOCD and CMSIS-SVD based peripheral register viewer written on Python

   Python 30 6

3. usb20dev usb20dev Public

   USB 2.0 FS Device controller IP core written in SystemVerilog

   SystemVerilog 31 12

4. pyhdlsim pyhdlsim Public

   Example of Python and PyTest powered workflow for a HDL simulation

   Python 14 1

5. proto245 proto245 Public

   🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)

   SystemVerilog 28 7

6. playhdl playhdl Public

   🪀 Tool to play with HDL (inspired by EdaPlayground)

   Python 4