Skip to content

Commit

Permalink
Initial public release v0.4.0
Browse files Browse the repository at this point in the history
  • Loading branch information
fharding1 committed Jul 10, 2020
1 parent 0f38ac6 commit 7ccb9d1
Show file tree
Hide file tree
Showing 31 changed files with 39,797 additions and 16,578 deletions.
6 changes: 6 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,10 @@ fp-info-cache
*.xml
*.csv

# Exported schematics
pcb/mainboard/*.pdf
pcb/ledboard/*.pdf

# Gerbers
*.zip
*gerber*
Expand Down Expand Up @@ -57,3 +61,5 @@ pcb/mainboard/gloworm.3dshapes/USB-A1SSW6--3DModel-STEP-56544.STEP
# Micro USB
# Download here: https://www.snapeda.com/parts/10118194-0001LF/Amphenol%20ICC/view-part/?welcome=home
pcb/mainboard/gloworm.3dshapes/10118194-0001LF--3DModel-STEP-56544.STEP

.vscode/settings.json
11 changes: 11 additions & 0 deletions README.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
# Gloworm

This repository contains the hardware source for the [Gloworm](https://gloworm.vision) mainboard and ledboard.

# License

Licensed under the CERN-OHL-P v2. See the [license](cern_ohl_p_v2.pdf) and the [guide](cern_ohl_p_v2_howto.pdf).

# Releases

Visit the [releases](https://github.com/gloworm-vision/gloworm/releases) page for exported Gerber files, BoMs, position files, and STEPs.
2,224 changes: 1,208 additions & 1,016 deletions pcb/ledboard/ledboard.kicad_pcb

Large diffs are not rendered by default.

Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
(module PinHeader_1x02_P2.54mm_Vertical_RoundRect (layer F.Cu) (tedit 5F05AA0A)
(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x02 2.54mm single row")
(fp_text reference REF** (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PinHeader_1x02_P2.54mm_Vertical_RoundRect (at 0 4.87) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_text user %R (at 0 1.27 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole roundrect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.25))
(pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
22 changes: 11 additions & 11 deletions pcb/ledboard/ledboard.pro
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
update=Thu 18 Jun 2020 02:15:20 AM PDT
update=Fri 10 Jul 2020 04:14:30 AM PDT
version=1
last_client=kicad
[general]
Expand All @@ -12,16 +12,6 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
Expand Down Expand Up @@ -252,3 +242,13 @@ uViaDrill=0.25
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=.
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

0 comments on commit 7ccb9d1

Please sign in to comment.