fix: fix yosys-optimizer using boolean gate mapping with abc -fast mode

Fixes #554 It appears that our custom liberty file was not providing delays for the cells, and that was causing an assertion failure in the ABC library. Since the tfhe-rs boolean gates are a subset of the standard cell library, just restrict the standard cells using `-g CELLTYPE, ...` flags. PiperOrigin-RevId: 619611385
google · Mar 27, 2024 · 3087478 · 3087478
1 parent 82782b3
commit 3087478
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Showing 5 changed files with 24 additions and 273 deletions.
diff --git a/lib/Transforms/YosysOptimizer/BooleanGateImporter.cpp b/lib/Transforms/YosysOptimizer/BooleanGateImporter.cpp
@@ -20,14 +20,16 @@ namespace heir {
 mlir::Operation *BooleanGateImporter::createOp(Yosys::RTLIL::Cell *cell,
                                                SmallVector<Value> &inputs,
                                                ImplicitLocOpBuilder &b) const {
-  auto op = llvm::StringSwitch<mlir::Operation *>(cell->type.substr(1))
-                .Case("inv", b.create<comb::InvOp>(inputs[0], false))
-                .Case("xnor2", b.create<comb::XNorOp>(inputs, false))
-                .Case("and2", b.create<comb::AndOp>(inputs, false))
-                .Case("xor2", b.create<comb::XorOp>(inputs, false))
-                .Case("nand2", b.create<comb::NandOp>(inputs, false))
-                .Case("nor2", b.create<comb::NorOp>(inputs, false))
-                .Case("or2", b.create<comb::OrOp>(inputs, false))
+  // standard cell names look like $_CELL_
+  auto op = llvm::StringSwitch<mlir::Operation *>(
+                cell->type.substr(2, cell->type.size() - 3))
+                .Case("NOT", b.create<comb::InvOp>(inputs[0], false))
+                .Case("XNOR", b.create<comb::XNorOp>(inputs, false))
+                .Case("AND", b.create<comb::AndOp>(inputs, false))
+                .Case("XOR", b.create<comb::XorOp>(inputs, false))
+                .Case("NAND", b.create<comb::NandOp>(inputs, false))
+                .Case("NOR", b.create<comb::NorOp>(inputs, false))
+                .Case("OR", b.create<comb::OrOp>(inputs, false))
                 .Default(nullptr);
   if (op == nullptr) {
     llvm_unreachable("unexpected cell type");

diff --git a/lib/Transforms/YosysOptimizer/YosysOptimizer.cpp b/lib/Transforms/YosysOptimizer/YosysOptimizer.cpp
@@ -87,13 +87,12 @@ stat;
 // $2: abc path
 // $3: yosys runfiles path
 // $4: abc fast option -fast
-// TODO(#554): Re-enable -fast mode.
 constexpr std::string_view kYosysBooleanTemplate = R"(
 read_verilog {0};
 hierarchy -check -top \{1};
 proc; memory; stat;
 techmap -map {3}/techmap.v; opt; stat;
-abc -exe {2} -liberty {3}/tfhe-rs_cells.liberty; stat;
+abc -exe {2} -g AND,NAND,OR,NOR,XOR,XNOR {4};
 opt_clean -purge; stat;
 rename -hide */c:*; rename -enumerate */c:*;
 hierarchy -generate * o:Y i:*; opt; opt_clean -purge;

diff --git a/lib/Transforms/YosysOptimizer/yosys/BUILD b/lib/Transforms/YosysOptimizer/yosys/BUILD
@@ -9,6 +9,5 @@ filegroup(
     name = "share_files",
     srcs = glob([
         "*.v",
-        "*.liberty",
     ]),
 )
diff --git a/lib/Transforms/YosysOptimizer/yosys/tfhe-rs_cells.liberty b/lib/Transforms/YosysOptimizer/yosys/tfhe-rs_cells.liberty
diff --git a/tests/yosys_optimizer/add_one.mlir b/tests/yosys_optimizer/add_one.mlir
@@ -1,5 +1,7 @@
-// RUN: heir-opt --yosys-optimizer --canonicalize --cse %s | FileCheck %s
+// RUN: heir-opt --yosys-optimizer --canonicalize --cse %s | FileCheck %s --check-prefix=CHECK --check-prefix=LUT
+// RUN: heir-opt --yosys-optimizer="abc-fast=True" --canonicalize --cse %s | FileCheck %s --check-prefix=CHECK --check-prefix=LUT-FAST
 // RUN: heir-opt --yosys-optimizer="mode=Boolean" --canonicalize --cse %s | FileCheck --check-prefix=CHECK --check-prefix=BOOL %s
+// RUN: heir-opt --yosys-optimizer="mode=Boolean abc-fast=True" --canonicalize --cse %s | FileCheck --check-prefix=CHECK --check-prefix=BOOL-FAST %s
 
 module {
   // CHECK-LABEL: @add_one
@@ -14,7 +16,16 @@ module {
         ins(%in, %one: !secret.secret<i8>, i8) {
         ^bb0(%IN: i8, %ONE: i8) :
             // CHECK-NOT: arith.addi
-            // BOOL-COUNT-7: comb.inv
+
+            // LUT-COUNT-11: comb.truth_table
+            // LUT-FAST-COUNT-13: comb.truth_table
+            // BOOL-COUNT-14: comb
+            // BOOL-FAST-COUNT-16: comb
+
+            // LUT-NOT: comb.truth_table
+            // LUT-FAST-NOT: comb.truth_table
+            // BOOL-NOT: comb
+            // BOOL-FAST-NOT: comb
             %2 = arith.addi %IN, %ONE : i8
             secret.yield %2 : i8
         } -> (!secret.secret<i8>)