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1. pequeno_riscv pequeno_riscv Public

   Pequeno aka pqr5 is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I

   SystemVerilog 16 1

2. pqr5asm pqr5asm Public

   PQR5ASM is a RISC-V Assembler compliant with RV32I

   Python 7 1

3. FIFOs FIFOs Public

   Register-based and RAM-based FIFOs designed in Verilog/System Verilog.

   SystemVerilog 11 3

4. skid_buffer skid_buffer Public

   Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.

   SystemVerilog 11 3

5. gcd_calculator gcd_calculator Public

   GCD calculator with APB Slave interface.

   SystemVerilog 1

6. debouncer debouncer Public

   Debouncer circuit in Verilog to filter glitches/bounces inherent in switches.

   SystemVerilog 4 1