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Add SystemVerilog.sv #1570

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esteezy wants to merge 1 commit into leachim6:main from esteezy:SystemVerilog

esteezy commented Apr 28, 2024

Adding a language

The code displays "Hello World" (tio.run may help for testing)
I have no association with the language
There are no copyright issues with this code
The language has not been added prior to this pull request
I have updated the README

Link to programming language:


          Added SystemVerilog.sv - Updated README to reflect addition

24cf2f6

esteezy changed the title ~~Added SystemVerilog.sv - Updated README to reflect addition~~ Added SystemVerilog.sv

esteezy changed the title ~~Added SystemVerilog.sv~~ Add SystemVerilog.sv

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