litex-hub / pythondata-cpu-vexiiriscv Public

Python module containing verilog files/generators for VexiiRiscv CPU (for use with LiteX).

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
pythondata_cpu_vexiiriscv		pythondata_cpu_vexiiriscv
.gitignore		.gitignore
MANIFEST.in		MANIFEST.in
Makefile		Makefile
README.md		README.md
requirements.txt		requirements.txt
setup.py		setup.py
test.py		test.py