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[SV][ExportVerilog] Add sv.func, sv.func.call{.procedural}, sv.func.dpi.import #6977

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@uenoku uenoku commented May 1, 2024

This PR adds operations sv.func, sv.func.call{.procedural} and sv.func.dpi.import to SV.

sv.func op is model as a mixture of func.func and hw.module. Similar to hw.module, sv.func can mix the order of input and output arguments. sv.func implements FunctionOpInterface and can declare a function by an empty body region like func.func

Code around PrepareForEmission is ported from #6559.

sv.func @fib(in %n : i32, out out : i32 {sv.func.explicitly_returned}) {
  %one = hw.constant 1 : i32
  %two = hw.constant 2 : i32
  %cond = comb.icmp bin ule %n, %one: i32
  %result = sv.logic : !hw.inout<i32>
  sv.if %cond {
    sv.bpassign %result, %n: i32 
  } else {
    %n1 = comb.sub %n, %one: i32
    %result1 = sv.func.call.procedural @fib(%n1) : (i32) -> i32
    %n2 = comb.sub %n, %two: i32
    %result2 = sv.func.call.procedural @fib(%n2) : (i32) -> i32
    %add = comb.add %n1, %n2: i32
    sv.bpassign %result, %add: i32 
  }
  %read = sv.read_inout %result: !hw.inout<i32>
  sv.return %read : i32
}
function automatic logic [31:0] fib(    // test.mlir:1:1
  input [31:0] n        // test.mlir:1:17
);

  logic           [31:0] _fib_0;        // test.mlir:12:16
  logic           [31:0] _fib_0_0;      // test.mlir:10:16
  logic           [31:0] result;        // test.mlir:5:13
  if (n <= 32'h1)       // test.mlir:2:10, :4:11, :6:3
    result = n; // test.mlir:7:5
  else begin    // test.mlir:6:3
    logic           [31:0] _GEN = n - 32'h1;    // test.mlir:2:10, :9:11
    logic           [31:0] _GEN_0 = n - 32'h2;  // test.mlir:3:10, :11:11
    _fib_0_0 = fib(_GEN);       // test.mlir:9:11, :10:16
    _fib_0 = fib(_GEN_0);       // test.mlir:11:11, :12:16
    result = _GEN + _GEN_0;     // test.mlir:9:11, :11:11, :13:12, :14:5
  end
  fib = result; // test.mlir:16:11, :17:3
endfunction

include/circt/Dialect/SV/SVStatements.td Outdated Show resolved Hide resolved
include/circt/Dialect/SV/SVStatements.td Outdated Show resolved Hide resolved
@uenoku uenoku force-pushed the dev/hidetou/sv-func branch 6 times, most recently from dd987b7 to e5c706f Compare May 8, 2024 11:05
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uenoku commented May 8, 2024

Changes except for ExportVerilog/Prepare are separated into #7003, #7004, #7005 and #7015 for review. I'll keep the PR open to show a big picture for functions and DPI.

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