Hardware-accelerated sorting algorithm in which unsorted data elements are presented serially and evaluated against the sorted collection of data elements in parallel. The algorithm is implemented on a Xilinx Zynq-7000 AP SoC XC7Z020-CLG484-1 found on the ZedBoard but does not use IP cores and can be implemented on any other FPGA.
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Hardware-accelerated sorting algorithm
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mmattioli/hardware-sort
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