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1. avsdpll_3v3 avsdpll_3v3 Public

   This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Intern…

   SourcePawn 15 6

2. avsddac_3v3 avsddac_3v3 Public

   Forked from xzlashutosh/avsddac_3v3

   This repository contains the design and simulation process and results of potentiometric digital to analog converter.

   PostScript

3. avsddac_3v3-1 avsddac_3v3-1 Public

   Forked from neethujohny/avsddac_3v3

   This repository contains a detailed description of a 10-bit potentiometric digital-to-analog converter. This work is carried out as a part of VSD Research Internship. The repository consists of all…

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4. avsdbgp_3v3 avsdbgp_3v3 Public

   Forked from avinashbellana/BandgapReference

   This repository will maintain simulation files and other relevant files on the Bandgap Reference IP worked on in the EICT IITG - VSD Summer Online Internship 2020

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5. pg2bitcomp pg2bitcomp Public

   Implementation of Power Gating technique in comparator for Low-power applications.

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6. avsdpll_3v3-1 avsdpll_3v3-1 Public

   Forked from eddygta17/avsdpll_3v3

   Analog IP of On-chip clock multiplier (PLL) using the OSU 180nm technology

   Verilog