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Bluespec, Inc.
- Framingham, MA, USA
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Forvis_RISCV-ISA-Spec
Forvis_RISCV-ISA-Spec PublicFormal specification of RISC-V Instruction Set
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ICFP2020_Bluespec_Tutorial
ICFP2020_Bluespec_Tutorial PublicTutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
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RISCV_Piccolo_v1
RISCV_Piccolo_v1 PublicImplementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
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RISCV_ISA_Spec_Tour
RISCV_ISA_Spec_Tour PublicTutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
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Learn_Bluespec_and_RISCV_Design
Learn_Bluespec_and_RISCV_Design PublicTextbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
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