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Handle RISC-V CPU Manufacturer and Brand using uarch in /proc/cpuinfo #904

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Handle RISC-V CPU Manufacturer and Brand using uarch in /proc/cpuinfo #904

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14 changes: 14 additions & 0 deletions lib/cpu.js
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Expand Up @@ -605,6 +605,9 @@ function cpuManufacturer(str) {
if (str.indexOf('Xen') >= 0) { result = 'Xen Hypervisor'; }
if (str.indexOf('tcg') >= 0) { result = 'QEMU'; }
if (str.indexOf('apple') >= 0) { result = 'Apple'; }
if (str.indexOf('sifive') >= 0) { result = 'SiFive'; }
if (str.indexOf('thead') >= 0) { result = 'T-Head'; }
if (str.indexOf('andestech') >= 0) { result = 'Andes Technology'; }

return result;
}
Expand Down Expand Up @@ -788,6 +791,17 @@ function getCpu() {
}
}

// Test RISC-V
if (util.getValue(lines, 'architecture') === 'riscv64') {
const linesRiscV = fs.readFileSync('/proc/cpuinfo').toString().split('\n');
const uarch = util.getValue(linesRiscV, 'uarch') || '';
if (uarch.indexOf(',') > -1) {
const split = uarch.split(',');
result.manufacturer = cpuManufacturer(split[0]);
result.brand = split[1];
}
}

// socket type
let lines2 = [];
exec('export LC_ALL=C; dmidecode –t 4 2>/dev/null | grep "Upgrade: Socket"; unset LC_ALL', function (error2, stdout2) {
Expand Down