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sidhantp1906/README.md
  • 👋 Hi, I’m @sidhantp1906
  • 👀 I’m interested in VLSI Systom on chip design
  • 🌱 I’m currently a student with enthusiasm in digital VLSI
  • 💞️ I’m looking to collaborate with VLSI teams/companies
  • 📫 reach me ..through linkedin -sidhant priyadarshi

Popular repositories

  1. 4-Request-First-Come-First-Serve-Arbiter 4-Request-First-Come-First-Serve-Arbiter Public

    4 request first come first serve arbiter design using verilog HDL

    Verilog 3 1

  2. binary-to-csd binary-to-csd Public

    verilog code to covert binary number into canonical signed digit(csd)

    Verilog 2

  3. RTC-Real-Time-Clock- RTC-Real-Time-Clock- Public

    Design of real time clock(RTC) using Verilog HDL

    Verilog 2

  4. TicTacToe TicTacToe Public

    TicTacToe game using verilog hdl and implementation in spartan-3 FPGA board

    Verilog 2 1

  5. Adcanced_Digital_Logic_Design-01fe19bec187 Adcanced_Digital_Logic_Design-01fe19bec187 Public

    Lab projects using Verilog HDL

    Verilog 2

  6. csd-multiplier-using-booth-technique csd-multiplier-using-booth-technique Public

    csd multiplier using booth technique in which i have converted binary multiplier into csd and multiplicand is binary.

    Verilog 1