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@riscv-steel

RISC-V Steel

riscv-steel
Netherlands

Hello, I'm Rafa (github.com/rafaelcalcada), a computer engineer from Brazil. I moved to the Netherlands a few years ago to work for Siemens' Electronic Design Automation branch. I love digital electronics and for the last 4 years I have been working on the development of RISC-V Steel.

RISC-V Steel was born in 2020 as the final project of my degree in computer engineering. My original goal was to develop a new RISC-V processor core that was simple, robust, and for use as a building block in larger projects, hence the name Steel. At the end of that year I released the first version of RISC-V Steel and then graduated.

Some time after its release, RISC-V Steel gained attention on GitHub, with daily visits and downloads. This motivated me to expand it into a free and open collection of RISC-V IP. A system-on-chip IP was added to the project, expanding the processor core design by adding modules for interfacing with external devices (via UART), tools for software development, and extensive documentation of its features.

By contributing you will be motivating me to work harder on RISC-V Steel, add new features and make it a source of production-ready IP for hardware developers.

@riscv-steel

Motivate me to work even harder. Buy equipament to test RISC-V Steel in new FPGA development boards.

Featured work

  1. riscv-steel/riscv-steel

    Free and open collection of RISC-V IP.

    Verilog 110

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