A simplified and standardized interface for Bitcoin ASICs.
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Updated
May 25, 2024 - Python
A simplified and standardized interface for Bitcoin ASICs.
Versatile Functional Bus Description Language compiler back-end written in Go.
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Haskell to VHDL/Verilog/SystemVerilog compiler
Efficient Library software for Miners and Pools
DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
📉 Providing enhanced visibility into short positions on the Australian Stock Exchange
VUnit is a unit testing framework for VHDL/SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Allo: A Programming Model for Composable Accelerator Design
C2pool: a C++ decentralized, DoS-resistant, Hop-Proof pool. Looking for testers...
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