Skip to content
@chipsalliance

CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

CHIPS Alliance Logo

🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 3.7k 571

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3k 1.1k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.2k 190

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 953 308

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 774 206

  6. firrtl firrtl Public

    Flexible Intermediate Representation for RTL

    Scala 694 175

Repositories

Showing 10 of 95 repositories
View all repositories