AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Updated
May 27, 2024 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Code generation tool for control and status registers
Network on Chip Implementation written in SytemVerilog
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Simple single-port AXI memory interface
Control and status register code generator toolchain
OPAE porting to Xilinx FPGA devices.
Open-Source AXI4 DMA Engine in SystemVerilog and Chisel
Common SystemVerilog RTL modules for RgGen
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
Implementation of the Advanced Encryption Standard in Chisel
Hardware and Software Co-design implementations
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