RISC-V Embedded Processor for Approximate Computing

This is an HTML/Javascript CPU simulator and assembler for the CPU I designed. Originally, I created this CPU on paper many years ago for a homework assignment in college. More recently, I implemented my design in the Logisim logic simulator, and eventually it ran on an FPGA.

A platform for learning and experimenting with logic circuits

Computer Architecture UIUC SP 2018

Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor

In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.

Aggreage of my past CPU designs.

This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.

Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme

Sample Verilog codes for digital circuits

The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.

This is an implementation of a simple CPU in Logisim and Verilog.

This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.

These are various files pertaining to a CPU I designed. Can be used in conjunction with my Logisim CPU youtube video series.

FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64

Emulator for custom computer architecture

Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python

A simple, Turing-complete and easy to recreate CPU architecture.

VHDL Design for a CPU

Bizzas CPU design