Image Processing Toolbox in Verilog using Basys3 FPGA
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Updated
Sep 19, 2023 - VHDL
Image Processing Toolbox in Verilog using Basys3 FPGA
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
The collective code required for completing a 4-year B.Tech Computer Science Engineering Course.
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Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA
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Low-cost industrial fruit classifier. uses state-of-the-art artificial vision technology to accurately and efficiently sort and grade fruits. The system is capable of identifying and distinguishing between different types and sizes of fruits
Digital Systems 2 Course [ECE 778] - CA4 - Spring 2023 - University of Tehran - Dr. Safari
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Lab dan TM Pengantar Sistem Digital (PSD) 2022/2023 Gasal
Neander++ (Neander extended) implementation and testing in VHDL for Digital Systems' 2nd assignment.
SUTD 2020 50.002 Computation Structures Code Dump
A collection of useful material and personal projects from the Computer and Informatics Engineering Bachelor's degree program at the University of Aveiro.
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