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hdl

Here are 591 public repositories matching this topic...

feddischson / de0_hps_example

Examples for the Terasic DE0-nano-SOC board

c cmake fpga vhdl verilog altera hdl bare-metal fpga-soc terasic-de0-nano-soc

Updated Mar 30, 2018
Makefile

artalukd / verilog_snippets

Code for Computer Architecture Lab

verilog computer-architecture hdl

Updated Dec 4, 2017
Verilog

akaps / nand2tetris

Solutions to coursework Nand2Tetris by Shimon Schocken and Noam Nisan https://www.nand2tetris.org/

nand2tetris hdl

Updated Aug 22, 2020
Hack

RVC

hotwolf / RVC

Reusable Verilog Components

library verilog hdl general purpose

Updated Jun 4, 2019
Verilog

Jauler / shitty_cpu

I was just curious about how CPU's worked...

cpu hardware vhdl logic hdl hw

Updated May 19, 2021
VHDL

sjkeller / smart-sensors-project

Verilog implementations of different simple tasks

fpga verilog alu hdl verilog-hdl yosys ice40 spi-protocol verilog-project

Updated Oct 10, 2022
Verilog

gonzafernan / advanced-digital-design

Resolución de laboratorios y guías prácticas asignadas en el curso de Diseño Digital Avanzado 2022.

fpga dsp jupyter-notebook python3 verilog vivado hdl digital-design filter-design

Updated Sep 25, 2022
Jupyter Notebook

melchisedech333 / verilog-experiments

👾 My studies with Verilog and notions of digital systems.

verilog icarus-verilog hdl verilog-hdl digital-systems verilog-project verilog-code digital-system-design verilog-examples digital-systems-design digital-systems-fundamentals

Updated Nov 2, 2022
Verilog

AtlasFPGA / COREFANTASMICO

Core creado por Miguel Angel

verilog hdl cyc1000 max1000

Updated Apr 4, 2023

sorousherafat / verilogen.py

a new method for verilog HDL code generation by templates, implemented using python and jinja2.

python template jinja2 verilog code-generation hdl

Updated May 3, 2023
Verilog

tiagosr / gategen

Racket-based hardware definition DSL for generating gateware for FPGAs, ASICs and the like

fpga racket dsl hdl fpga-programming racket-languages asic-design

Updated Nov 28, 2023
Racket

estbeetoo / node-red-contrib-hdl

HDL for Node-RED, utilizing pure JavaScript HDL Buspro driver

javascript smarthome node-red smart-home hdl nodered

Updated Apr 29, 2017
HTML

TommyDaiJ / iOS-HDL-SDK-Demo

This example is to demonstrate HDL's iOS SDK, which can realize search device, control device, acquire device status, receive device status change push, etc.

Updated May 25, 2018
Swift

the-snowwhite / mksocfpga3

For finalizing experimental development work on the mksocfpga_hm3 repo back into machinekit

linux cnc vivado systemverilog motion-controllers hdl 3d-printing milling quartus-prime

Updated Jan 2, 2018
SystemVerilog

denporras / CE3201-TrainController

En este laboratorio se requiere que el grupo de trabajo diseñe, implemente en un HDL y demuestre su funcionamiento con un kit FPGA, un controlador para un sistema de dispositivos de señalización y prevención (semáforo y agujas) para un cruce de vía vehicular - ferroviaria . Este controlador estará basado en una máquina de estados finitos (FSM), …

fpga verilog finite-state-machine xilinx hdl spartan

Updated Sep 22, 2017
C

WAR10CKBS / SimonGame

Simon Game Implementation in Verilog

simon-game verilog hdl simonsays

Updated Jul 9, 2019
Verilog

tsheinen / nand2tetris-hdl-parser

parser nand2tetris hdl

Updated Aug 25, 2021
Rust

iovcc.github.io

iovcc / iovcc.github.io

An International Obfuscated *HDL Code Contest (Why Verilog? For the name to be good: IOVCC)

vhdl verilog hdl vhdl-code vhdl-examples verilog-code verilog-examples

Updated Apr 28, 2021
HTML

iDoka / statistics-acquisition-module

Statistics Acquisition Module on Verilog

statistics asic generator fpga gdb rtl debug verilog xilinx hdl vlsi axi amba

Updated Jun 21, 2021

bigoh1 / nand2tetris

My playground for nand2tetris course

Updated Jul 28, 2021
Assembly

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