HDL libraries and projects
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Updated
May 23, 2024 - Verilog
HDL libraries and projects
PlutoSDR Firmware
VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.
A modern hardware definition language and toolchain based on Python
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Hardware Description Languages
This Repository invites freelancer friendly neighbourhood developers to contribute to open source .
Test suite designed to check compliance with the SystemVerilog standard.
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
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