奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

Logisim实现的五级流水线MIPS CPU

Onion Omega 2 IoT MIPS32LE projects

a simple MIPS CPU for the Fundamental Experiment of Digital Logic and Processor course of EE, Tsinghua University

A Verilog implementation of a pipelined MIPS processor

BUAA Computer Organization Project8 FPGA

MIPS CPU in verilog

Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.

BUAA Computer_Organizations Projects

An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler

University of Pittsburgh ECE 1195

32-bit pipelined MIPS CPU using Verilog with booth multiplication algorithm (faster multiplication in hardware). Xilinx Sesign Suite

BUAA Computer Organization Project4 CPU monocycle

Simple single cycle processor for modified reduced MIPS32 instruction set.

a 32-bit MIPS instruction set CPU's design and realization based on Logisim Platform

BUAA Computer Organization Project5 CPU pipeline

Verilog Description for a 32bit MIPS Processor

BUAA Computer Organization Project7 CPU pipeplus

MIPS written in System Verilog

Bluespec implementation of PG routing algorithm on a network on chip running a SMIPS