Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
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Updated
Sep 17, 2022
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
The SAP-1 in Verilog, and now as an ASIC!
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry
This is part of EC383 - Mini Project in VLSI Design.
2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
This is my openlane repository in which we perform synthesis of our design/module.
VSDMemSOC Implementation flow:: RTL2GDSII
Adding a Customized Standard Cell into the OpenLane Flow
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