A superscalar out-of‐order architectural simulator (With Memory Hierarchy).
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Updated
Dec 10, 2016 - Java
A superscalar out-of‐order architectural simulator (With Memory Hierarchy).
Compiler written in steps
Arduino example sketches demonstrating ADC Single Conversion, ADC in Free Running mode, ADC with Noise Reduction, ADC with Frequency tuning, PWM in Fast mode, Other PWM modes, 16bit Timer1 example, and a Watchdog example using an interrupt and/or system reset.
Let's start short esoteric journey.
Register machine interpreter written in C
Stack based virtual machine with it's own language
Why do we need a memory model
Generate boilerplate code of C macro definition for all registers and their fields of a chip.
Parse register dumps with minimal overhead
Simulation of Designs of Basic Computer & Processor Architecture(4-bit MIPS CPU, Floating Point Adder) in Logisim as assignments of Computer Architecture Sessional course of CSE 306 of CSE, BUET
rpi-internal-registers-online - http://paulwratt.github.io/rpi-internal-registers-online/
Mini Project from COL215 course (Digital Logic and System Design) by Prof. Anshul Kumar
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