Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
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Updated
Jul 28, 2023 - Verilog
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
SystemRDL 2.0 language compiler front-end
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
C++ 17 Hardware abstraction layer generator from systemrdl
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
SystemRDL lexer for Pygments syntax highlighting
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