wishbone-bus
Here are 27 public repositories matching this topic...
Plasma MIPS (I) SoC
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Sep 17, 2018 - C
Forth CPU J1 in SystemVerilog and Wishbone interface
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Oct 3, 2018 - SystemVerilog
A System on a Chip Implementation for the XuLA2-LX25 board
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Dec 13, 2018 - Verilog
Trying to learn Wishbone by implementing few master/slave devices
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Jan 7, 2019 - SystemVerilog
Trying to implement a soft core SoC
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Apr 6, 2019 - Verilog
RISC-V Ibex core with Wishbone B4 interface
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Dec 24, 2019 - HTML
A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91
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Nov 6, 2020 - Python
A collection of formal properties for hardware buses, and cores using them.
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Feb 22, 2021 - Verilog
Simple UART controller for FPGA written in VHDL
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Aug 7, 2021 - VHDL
Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.
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Apr 23, 2023 - VHDL
Bus bridges and other odds and ends
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Jan 12, 2024 - Verilog
A wishbone controlled scope for FPGA's
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Jan 12, 2024 - Verilog
A wishbone controlled FM transmitter hack
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Jan 16, 2024 - Verilog
A utility for Composing FPGA designs from Peripherals
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Jan 18, 2024 - C++
A collection of debugging busses developed and presented at zipcpu.com
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Jan 18, 2024 - Verilog
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